• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    The invention relates to a method for producing bipolar transistors and MOS transistors, comprising the following steps: a) providing a semiconductor layer on an insulating layer (22); on the side of the bipolar transistors: b) forming an insulating region comprising said insulating layer and extending to the upper face; c) etching apertures through said insulating region, thereby delimiting insulating walls (58); d) filling the openings with first epitaxial portions (60); and e) doping the first epitaxial portions and a first region (96) extending under the first epitaxial portions and under the insulating walls; on the side of the bipolar transistors and the side of the MOS transistors: f) forming gate structures (100); g) forming second epitaxial portions; and h) doping the first type of conductivity of the second epitaxial portions covering the first epitaxial portions.
    公开号:FR3049111A1
    申请号:FR1652379
    申请日:2016-03-21
    公开日:2017-09-22
    发明作者:Olivier Weber；Emmanuel Richard；Philippe Boivin
    申请人:Commissariat a lEnergie Atomique CEA；STMicroelectronics Crolles 2 SAS；STMicroelectronics Rousset SAS；Commissariat a lEnergie Atomique et aux Energies Alternatives CEA；
    IPC主号:
    专利说明:

    METHOD FOR MAKING MOS AND BIPOLAR TRANSISTORS
    Field
    The present application relates to methods for manufacturing electronic chips, and more particularly to a method of realization in CMOS technology of vertical bipolar transistors.
    Presentation of the prior art
    Electronic chips contain both logic circuits and phase change memory circuits. The logic circuits include many MOS transistors. The memory circuits include memory points arranged in a matrix, and each memory point is associated with a vertical bipolar transistor. This transistor is used to program, erase or read each memory point independently. The bipolar transistors corresponding to the memory points of the same row or row of the matrix have their common base. The memory points of the same column of the matrix are arranged between the emitter of the corresponding bipolar transistor and a common upper metallization. When it is desired to program, erase or read a memory point, the bipolar transistors of the corresponding row are made to pass and a voltage is applied to the upper metallization of the corresponding column. A current of programming, erasing or reading of the memory point is thus circulated in the memory point.
    Conventional methods have been proposed for producing in one part of a chip complementary MOS transistors and, in another part of the chip, vertical bipolar transistors that can be controlled by a common base. These methods pose various problems of implementation.
    There is a need for a simple method compatible with conventional CMOS technology, making it possible simultaneously to produce complementary MOS transistors and bipolar transistors having a common base. summary
    Thus, an embodiment provides a method for producing vertical bipolar transistors and MOS transistors, comprising the following steps: a) providing a semiconductor layer disposed on an insulating layer covering a semiconductor substrate of a first conductivity type; on the side of the bipolar transistors: b) forming an insulating region comprising said insulating layer and extending to the upper face of the assembly; c) etching openings reaching the substrate through said insulating region, thereby delimiting insulating walls; d) selectively epitaxially forming a semiconductor to fill the openings with first epitaxial portions; and e) doping a second conductivity type of the first epitaxial portions and a first region extending in the upper portion of the substrate under the first epitaxial portions and under the insulating walls; on the side of the bipolar transistors and the side of the MOS transistors: f) forming gate structures; g) forming by selective epitaxy the second epitaxial semiconductor portions; and h) doping the first type of conductivity of the second epitaxial portions covering the first epitaxial portions.
    According to one embodiment, in step c) the openings are etched at a gate pitch of the MOS transistors and in step f) the gate structures are formed at said gate pitch.
    According to one embodiment, step b) comprises a step of oxidizing the semiconductor layer over its entire thickness.
    According to one embodiment, step b) comprises a step of removing the semiconductor layer over its entire thickness.
    According to one embodiment, the method further comprises, before step f), an isolation trenching step defining the first region.
    According to one embodiment, step f) comprises a step of forming insulating lateral spacers included in the grid structures.
    According to one embodiment, the method further comprises a step of forming vias arranged on the second epitaxial portions, followed by a step of forming phase transition memory points disposed on the vias.
    According to one embodiment, the semiconductor layer is made of silicon.
    According to one embodiment, the semiconductor layer has a thickness of less than 20 nm.
    According to one embodiment, the insulating walls have a thickness of between 25 and 30 nm.
    According to one embodiment, the insulating walls extend as deeply as the insulating layer.
    According to one embodiment, the gate pitch is between 80 and 150 nm.
    Another embodiment provides the device comprising: vertical bipolar transistors having a common collector region covered by a common base region, and upper emitter regions separated by first gate structures having lateral spacers, the structures grid gate based on insulating walls extending vertically in an upper portion of the base region; and MOS transistors each comprising drain and source regions having epitaxial upper portions separated by a second gate structure identical to the first gate structures, the first and second gate structures being arranged regularly, the upper emitter regions and the drain and source regions having upper faces disposed at identical levels to within 10 nm.
    According to one embodiment, the first and second grid structures are arranged in a same grid step.
    According to one embodiment, the MOS transistors are arranged on an insulating layer, the insulating walls extending in the substrate as deeply as the insulating layer.
    Brief description of the drawings
    These and other features and advantages will be set forth in detail in the following description of particular embodiments made without implied limitation in relation to the appended figures among which: FIG. 1 is a sectional, partial and schematic view of a portion of an electronic chip comprising bipolar transistors; Figures 2 to 11 are partial sectional and schematic views illustrating steps of an embodiment of a method for manufacturing vertical bipolar transistors and MOS transistors; and Fig. 12 is a schematic top view illustrating a step of an embodiment of a method for manufacturing bipolar transistors.
    detailed description
    The same elements have been designated by the same references in the various figures and, in addition, the various figures are not drawn to scale. For the sake of clarity, only the elements useful for understanding the described embodiments have been shown and are detailed.
    In the following description, when reference is made to absolute position qualifiers, such as the terms "left", "right", etc., or relative, such as "on", "under", " above, "below", "upper", "lower", etc., or with qualifiers for orientation, such as the term "vertical", etc., reference is made to the orientation of the element concerned. in the figures concerned. Unless stated otherwise, the term "insulator" refers to electrically insulating elements.
    FIG. 1 is a partial, schematic sectional view of a portion of an electronic chip 1 comprising bipolar transistors and resistive memory points, for example with a phase change. The chip 1 comprises a p-type doped silicon substrate 3. An N-type doped region 5 is situated in the upper part of the substrate 3 and is delimited, on the left in the figure, by an isolation trench. 9 p-type dopants extend in the upper part of the region 5 and are regularly positioned at a pitch D. The P 9 regions are separated by superficial isolation trenches 10. The isolation trenches 10 extend vertically in the N 5 region to a level below the lower level of the P 9 regions. The N 5 region is provided with an N + 11 contact zone connected to an application node of a potential V g.
    MOS transistor gate structures 12 are arranged regularly on the upper surface of the isolation trenches 7 and 10 at the same pitch D as the superficial trenches 10. Each gate structure 12 has lateral spacers 13. Each P 9 region is connected via a via 14 to a phase change memory point located above the via 14. Each memory point comprises under a higher metallization 15 a phase change material 16 and a resistive element 17 surrounded by an insulator 18 and located between the material 16 and the via 14. Three memory points Ml, M2 and M3 are represented in FIG. 1 and correspond to memory points of a row of memory points arranged in a matrix. The upper metallizations of memory points M1, M2 and M3 are coupled to respective potential application nodes V1, V2, V3 by contacts 19.
    The lower part of the P-type doped substrate 3, the N-type doped region and the P-type doped regions 9 constitute vertical PNP type bipolar transistors. Each region P 9 constitutes an upper emitter region of a bipolar transistor. Region N 5 is a common base region, and the lower portion of the substrate is a common collector. This common collector is connected to a GND ground.
    To program or erase the memory point M1, a low level of potential Vg is applied to the common base region. Applying a selected high level of the potential VI allows a programming or erasing current to flow in the resistive element of the memory point M1. This results in a heating and a phase change of the phase change material of the memory point M1. The use of vertical bipolar transistors makes it possible to circulate high programming or erasing currents, for example greater than 100 μs, over a small area, allowing the integration of high density memories. The presence of superficial isolation trenches makes it possible to limit the flow of leakage currents from the emitter region 9 associated with the memory point M1 to the neighboring memory points. These leakage currents are due in particular to the presence of parasitic bipolar transistors formed by the P 9 regions of neighboring transistors separated by the base region 5.
    It is desired to simultaneously realize, in a manner compatible with CMOS technology, lateral MOS transistors and vertical bipolar transistors. The MOS transistors may be logic circuit transistors and the bipolar transistors may be transistors of nonvolatile memory points that it is desired to isolate correctly from each other. It is desired to obtain bipolar transistors having a common base and which are separated from each other by insulating structures such as superficial trenches.
    Figures 2 to 11 are sectional, partial and schematic views illustrating steps of an embodiment of a method for simultaneously manufacturing vertical bipolar transistors and MOS transistors. Each figure illustrates, on the right side, the realization of the vertical bipolar transistors and, on the left side, the realization of the MOS transistors. At the step illustrated in FIG. 2, there is provided a SOI-type semiconductor-on-insulator structure, comprising, on a semiconductor substrate, for example in P-type doped silicon, an insulating layer 22 on which a semiconductor layer extends. 24, for example silicon. The SOI structure is covered with an etching stop layer 26, for example made of silicon oxide. A layer of silicon nitride 28 is then deposited. By way of example, the semiconductor layer 24 has a thickness of less than 20 nm. The etch stop layer may be less than 5 nm thick. In the step illustrated in FIG. 3, a resin mask 30 has been formed on the left side of the upper surface of the layer 28. The right part of the silicon nitride layer is then eliminated by etching stopping at the stop layer 26. In the step illustrated in FIG. 4, the mask 30 was removed. Thermal oxidation of the upper face of the structure is then performed so as to oxidize the right portion of the semiconductor layer 24 on the the whole of its thickness. The straight portions of the insulating layers 22 and 26 and the oxidized portion of the layer 24 constitute an insulating region 40 on the right side. The region 40 extends from the lower level of the layer 22 to the upper face of the structure. The left part of the layer 28 constitutes a hard mask 42 which makes it possible to keep the left part of the semiconductor layer 24 intact. As a variant of the step illustrated in FIG. 4, after removing the mask 30, it is possible to eliminate by etching the layer 26 and the semiconductor layer 24 over its entire thickness. An insulating region 40 is obtained which then corresponds to the right part of the layer 22. In the step illustrated in FIG. 5, a resin mask 50 is formed comprising in the right part openings 52 arranged at the regular grid pitch D of network of MOS transistors gates to be fomé later. By an etching step, the openings 52 are then extended vertically by openings 56 through the insulating portion 40 into the upper part of the substrate 20. The openings 56 thus define insulating walls 58 arranged regularly at the gate pitch D By way of example, the gate pitch D is between 80 nm and 150 nm. By way of example, the distance separating two adjacent openings 56, or width of the insulating walls, is between 20 and 40 nm. For example, the thickness or height of the insulating walls is between 25 and 30 nm. The insulating layer 22 may have a thickness of 25 nm. In the step illustrated in Figure 6, the mask 50 was first removed. We then proceed to a selective epitaxy of silicon. Epitaxial portions 60 are formed from the bottom of the openings 56, and grow between the insulating walls 58. The epitaxy is stopped when the epitaxial portions 60 fill the apertures 56 to the upper level of the insulating walls 58. At step illustrated in FIG. 7, the hard mask 42 has been removed. A multilayer 70 comprising a silicon oxide layer and a silicon nitride layer is then deposited on the upper surface of the entire structure. In the step illustrated in FIG. 8, a mask 80 has been made on the upper surface of the assembly of the structure.
    Trenches are formed to a level in the substrate 20. A trench 84 separates the left side corresponding to the MOS transistors and the right side corresponding to the bipolar transistors. Trenches 84 may also separate on the right side portions each corresponding to a group of bipolar transistors having a common base. Trenches 86 for separating the MOS transistors are located on the left side. In the step illustrated in FIG. 9, the trenches 84 and 86 have been filled with silicon oxide, forming respective isolation trenches 90 and 92. The mask 80, the multilayer 70 and the isolation trench portions 90 and 92 located above the lower level of the multilayer 70 have been removed. On the left side, the remaining portions of the etch stop layer 26 were then removed. The remaining portions of the semiconductor layer 24 constitute slabs or semiconducting active areas 94 (or thin semiconductor films) resting on the insulating layer 22 and separated by isolation trenches 92. The right-hand side is then subjected to doping. By ion implantation to form a doped region 96 which extends from the upper surface in the epitaxial portions 60 and into the substrate 20, to a level in the substrate above the lower level of the trenches; isolation. The N-type doped region 96 extends below the insulating walls 58. In the step illustrated in FIG. 10, a grid of grids 100 regularly spaced at the grid pitch D is formed simultaneously on the right-hand side and on the left-hand side. is provided on its flanks with insulating lateral spacers 102. The grid structures 100 have been positioned, on the right side, on the insulating walls 58 to form separating elements and, on the left side, in a central position on the slabs 94 to constitute the grids of MOS transistors.
    A selective silicon epitaxy is then made on the surface of the entire structure, simultaneously on the right and left sides. On the left side, epitaxial portions 104 are formed from the portions of the semiconductor slabs 94 located on either side of the gate structures 100. On the right side, epitaxial portions 106 grow between the insulating spacers 102 from the upper face of the Portions 60 of the N 96 region. The epitaxial portions 106 and the epitaxial portions 104 have top faces at levels equal to 10 μm. In the step illustrated in FIG. 11, a left-side N-type doping was first carried out in the epitaxial portions 104 and portions of the slabs 94 situated beneath these epitaxial portions, and on the right side in FIG. 114 of the epitaxial portions 106. Thus, drain and source regions 110 of N-channel MOS transistors are obtained, the portions of the slabs 94 located under the gates constituting channel forming regions 112 of the MOS transistors. A contact zone 114 associated with the N 96 region has also been obtained. The P-type doping of the epitaxial portions 106 is then carried out on the right side. The upper portions of the epitaxial portions 60 of the regions 96 can also be doped. p-type 116 doped regions.
    On the right side, bipolar transistors of the vertical PNP type were obtained. Each P region 116 constitutes an upper emitter region of a bipolar transistor. The N 96 region is a common base region, and the lower portion of the P substrate 20 is a common collector. The upper emitter regions 116 of the bipolar transistors are separated in particular by the gate structures 100. The gate structures electrically isolate the upper emitter regions 116 by virtue of the presence of the insulating lateral spacers 102. the insulating wall 58 situated beneath it an insulating structure 118 which separates adjacent emitter regions 116 and extends vertically in an upper part of the common base region 96. The insulating structures 118 thus make it possible to limit the flow of currents of leakage between neighboring bipolar transistors. These leakage currents are due to the presence, in particular, of a parasitic bipolar transistor between a zone P 116, an adjacent zone N 60 and another zone P 116, adjacent to zone N 60. At a later stage, not shown, vias are formed on the drain and source areas 110 of the MOS transistors and the emitter regions 116 of the bipolar transistors. It should be noted that the drain and source zones 110 and the emitter regions 116 have upper faces situated at substantially identical levels, which allows a particularly simple embodiment of the vias. Resistive memory points, for example with a phase change, can then be formed on the vias. Each memory point is located on a via disposed on one of the emitter regions 116 and covered with a higher metallization.
    It should be noted that the isolation trenching steps illustrated in FIGS. 7, 8 and 9, the epitaxial step illustrated in FIG. 10 and the doping steps illustrated in FIG. 11 are steps of embodiment included in a method of FIG. manufacturing MOS transistors on an SOI structure. In addition, such a method for producing MOS transistors may comprise a step of etching apertures of the insulating layer of the SOI structure, for example to make contacts with the substrate of the SOI structure. This etching can be performed at the same time as the etching step illustrated in FIG. 5. Thus, the described embodiments allow the fabrication of isolated bipolar transistors by adding a reduced number of steps to a method of manufacturing MOS transistors on an SOI structure.
    In the described embodiments, the manufacture of a single group of vertical bipolar transistors having a common base is described. Other embodiments are possible for manufacturing a plurality of groups of bipolar transistors.
    FIG. 12 is a schematic top view illustrating an embodiment of a method of manufacturing such a plurality of transistor groups 120, the transistors of each group 120 having a common base and corresponding to a row of a matrix resistive memory points. FIG. 12 is a view at the step illustrated in FIG. 9, before the grids 100 are formed. The common base regions 96 of the neighboring groups 120 are separated by isolation trenches 90. There are the isolation walls 58 located in each common base region.
    Particular embodiments have been described. Various variations and modifications will be apparent to those skilled in the art. In particular, in the embodiments described, the left side of the structure obtained contains only N-channel MOS transistors. In practice, P-channel MOS transistors will also be manufactured. These transistors have drain and source zones. which can be realized at the same time as the emitter regions 116 of the bipolar transistors.
    In the described embodiments, the bipolar transistors are of the PNP type and made from an SOI type structure on a P-type substrate. Other embodiments may correspond to the embodiments described in which the types of N and P conductivity are reversed.
    In addition, although, in the embodiments described, a semiconductor layer of silicon covers an insulator of an SOI structure, the semiconductor layer may be of another semiconductor material.
    Although embodiments have been described in which MOS transistors are produced, it is possible to produce, next to the bipolar transistors, any other type of SOI transistor, for example double gate transistors, for example of the type FinEET.
    权利要求:
    Claims (15)
    [1" id="c-fr-0001]
    A method for producing vertical bipolar transistors and MOS transistors, comprising the following steps: a) providing a semiconductor layer (24) disposed on an insulating layer (22) covering a semiconductor substrate (20) of a first conductivity type ; on the side of the bipolar transistors: b) forming an insulating region (40) comprising said insulating layer and extending to the upper face of the assembly; c) etching apertures (56) reaching the substrate through said insulating region, thereby defining insulating walls (58); d) selectively epitaxially forming a semiconductor to fill the openings with first epitaxial portions (60); and e) doping a second conductivity type of the first epitaxial portions and a first region (96) extending in the upper portion of the substrate under the first epitaxial portions and under the insulating walls; on the side of the bipolar transistors and the side of the MOS transistors: f) forming gate structures (100); g) selectively epitaxializing the second epitaxial semiconductor portions (104, 106); and h) doping the first conductivity type of the second epitaxial portions (106) covering the first epitaxial portions.
    [2" id="c-fr-0002]
    2. Method according to claim 1, wherein in step c) the openings (56) are etched at a gate pitch (D) of the MOS transistors and in step f) the gate structures (100) are fortified audit no grid.
    [3" id="c-fr-0003]
    3. Method according to claim 1 or 2, wherein step b) comprises a step of oxidation of the semiconductor layer (24) over its entire thickness.
    [4" id="c-fr-0004]
    4. Method according to any one of claims 1 to 3, wherein step b) comprises a step of removing the semiconductor layer (24) over its entire thickness.
    [5" id="c-fr-0005]
    The method of any one of claims 1 to 4, further comprising, prior to step f), an isolation trenching step (90, 92) defining the first region.
    [6" id="c-fr-0006]
    The method of any one of claims 1 to 5, wherein step f) comprises a step of forming insulative lateral spacers (102) included in the gate structures (100).
    [7" id="c-fr-0007]
    7. Method according to any one of claims 1 to 6, further comprising a vias formation step disposed on the second epitaxial portions, followed by a step of fomation of phase transition memory points disposed on the vias.
    [8" id="c-fr-0008]
    The method of any one of claims 1 to 7, wherein the semiconductor layer (24) is silicon.
    [9" id="c-fr-0009]
    The method of any one of claims 1 to 8, wherein the semiconductor layer (24) has a thickness of less than 20 nm.
    [10" id="c-fr-0010]
    10. A method according to any one of claims 1 to 9, wherein the insulating walls (58) have a thickness between 25 and 30 nm.
    [11" id="c-fr-0011]
    The method of any one of claims 1 to 10, wherein the insulating walls extend as deeply as the insulating layer (22).
    [12" id="c-fr-0012]
    The method of any one of claims 1 to 11, wherein the gate pitch (D) is between 80 and 150 nm.
    [13" id="c-fr-0013]
    A device comprising: vertical bipolar transistors having a common collector region (20) covered by a common base region (96), and emitter upper regions (114) separated by first gate structures (100) provided with lateral spacers (102), the grid structures resting on insulating walls (58) extending vertically in an upper portion of the base region; and MOS transistors each comprising drain and source regions (110) having epitaxial upper portions separated by a second gate structure (100) identical to the first gate structures, the first and second gate structures being arranged regularly, the upper emitter regions and the drain and source regions having upper faces disposed at identical levels to within 10 nm.
    [14" id="c-fr-0014]
    14. Device according to claim 13, wherein the first and second grid structures are arranged in a same grid step (D).
    [15" id="c-fr-0015]
    15. Device according to claim 13 or 14, wherein the MOS transistors are arranged on an insulating layer (22), the insulating walls (58) extending in the substrate as deeply as the insulating layer.
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    法律状态:
    2017-02-22| PLFP| Fee payment|Year of fee payment: 2 |
    2017-09-22| PLSC| Publication of the preliminary search report|Effective date: 20170922 |
    2018-02-20| PLFP| Fee payment|Year of fee payment: 3 |
    2020-02-20| PLFP| Fee payment|Year of fee payment: 5 |
    2021-02-19| PLFP| Fee payment|Year of fee payment: 6 |
    2022-02-18| PLFP| Fee payment|Year of fee payment: 7 |
    优先权:
    申请号 | 申请日 | 专利标题
    FR1652379|2016-03-21|
    FR1652379A|FR3049111B1|2016-03-21|2016-03-21|METHOD FOR MAKING MOS AND BIPOLAR TRANSISTORS|FR1652379A| FR3049111B1|2016-03-21|2016-03-21|METHOD FOR MAKING MOS AND BIPOLAR TRANSISTORS|
    US15/454,788| US9929146B2|2016-03-21|2017-03-09|Method of forming MOS and bipolar transistors|
    US15/897,524| US10381344B2|2016-03-21|2018-02-15|Method of forming MOS and bipolar transistors|
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